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description cxd1172am/ap is a 6-bit cmos a/d converter for video use. the adoption of a 2-step parallel system achieves low consumption at a maximum conversion speed of 20msps minimum, 35msps typical. features ? resolution: 6-bit 1/2lsb ? max. sampling frequency: 20msps ? low power consumption: 40mw (at 20msps typ.) (reference current excluded) built-in sampling and hold circuit. 3-state ttl compatible output. power supply: 5v single low input capacitance: 4pf reference impedance: 250 (typ.) applications tv, vcr digital systems and a wide range of fields where high speed a/d conversion is required. structure silicon gate cmos monolithic ic absolute maximum ratings (ta = 25?) supply voltage v dd 7v reference voltage v rt , v rb v dd + 0.5 to v ss ?0.5 v input voltage v in v dd + 0.5 to v ss ?0.5 v (analog) input voltage v clk v dd + 0.5 to v ss ?0.5 v (digital) output voltage v oh , v ol v dd + 0.5 to v ss ?0.5 v (digital) storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 4.75 to 5.25 v reference input voltage v rb 0 to 4.1 v v rt 0.9 to 5.0 v v rt ?v rb 0.9 to av dd v analog input voltage v in v rb to v rt v clock pulse width t pw1 , t pw0 23ns (min.) to 1.1s (max.) operating temperature topr ?0 to +75 ? ?1 e89320c78-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxd1172am/ap 6-bit 20msps video a/d converter (cmos) cxd1172am 16 pin sop (plastic) cxd1172ap 16 pin dip (plastic)
?2 cxd1172am/ap block diagram and pin configuration pln description and equivalent circuits reference voltage lower sampling comparators (3bit) lower sampling comparators (3bit) upper sampling comparators (3bit) lower encoder (3bit) lower encoder (3bit) upper encoder (3bit) lower data latchs upper data latchs clook generator 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 1 av ss dv dd av dd vrb v in av dd dv dd vrt d 0 d 1 d 2 clk d 3 d 5 dv ss d 4 no. symbol equivalent circuit description d 0 (lsb) to d 5 (msb) output 1 to 6 d 0 to d 5 di analog input 12 v in 12 av dd av ss analog gnd 16 av ss clock input 7 8 9, 15 10, 14 dv ss dv dd av dd digital gnd digital +5v analog +5v clk dv dd 7 dv ss reference voltage (top) reference voltage (bottom) 11 13 vrt vrb 13 11 av dd av ss
?3 cxd1172am/ap clock data output analog input t pw1 t pw0 n n + 1 n + 2 n + 3 n + 4 n ?3 n ?2 n ?1 n n + 1 td = 18ns : point for analog signal sampling. timing chart 1 input signal voltage step digital output code msb lsb v rt v rb 0 31 32 63 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 digital output compatibility between analog input voltage and the digital output code is indicated in the chart below. .............. ... ... ... ...
?4 cxd1172am/ap electrical characteristics (v dd = 5v, v rb = 1.0v, v rt = 2.0v, ta = 25?) conversion speed supply current reference pin current analog input band width (?db) analog input capacitance reference resistance (v rt to v rb ) offset voltage * 1 digital input voltage digital input current digital output current output data delay integral non-linearity error differential non-linearity error differential gain error differential phase error aperture jitter sampling delay 0.5 3 175 0 15 4.0 ?.1 3.7 v dd = 4.75 to 5.25v ta = ?0 to +75? v in = 1.0 to 2.0v f in = 1khz ramp fc = 20msps ntsc ramp wave input envelope v in = 1.5v + 0.07vrms potential difference to vrt potential difference to vrb v dd = 4.75 to 5.25v ta = ?0 to +75? v dd = max. v dd = min. with ttl 1 gate and 10pf load ta = ?0 to +75? v dd = 4.75 to 5.25v end point ntsc 40 ire mod ramp fc = 14.3msps 7 4 18 4 250 ?0 35 18 0.3 0.3 1.0 1.0 40 4 20 12 5.7 325 ?0 55 1.0 5 5 30 0.5 0.5 msps ma mhz pf mv v ? ma ns lsb % deg ps ns item symbol conditions min. typ. max. unit * 1 the offset voltage eob is a potential difference between vrb and a point of position where the voltage drops equivalent to 1/2 lsb of the voltage when the output data changes from "00000000" to "00000001". eot is a potential difference between vrt and a potential of point where the voltage rises equivalent to 1/2 lsb of the voltage when the output data changes from "11111111" to "11111110". v ih = v dd v il = 0v v oh = v dd + 0.5v v ol = 0.4v fc i dd i ref bw c in r ref e ot e ob v ih v il i ih i il i oh i ol t dl e l e d dg dp taj tsd
?5 cxd1172am/ap integral non-linearity error differential non-linearity } test circuit offset voltage cxd1172a a < b a > b comparator buffer dvm controller clk (20mhz) s 1 : on if a < b s 2 : on if b > a a6 a1 to a0 b6 b1 b0 ? +v s 2 s 1 6 6 6 ? ? 000 ? 00 to 111 ? 0 v in to maximum operational speed differential gain error } test circuit differential phase error s. g. ntsc signal source s. g. (cw) ttl ecl cxd 1172a 10bit d/a ttl ecl counter error rate vector scope h. p. f 1 2 620 ?.2v cx20202a-1 ?.2v clk 6 6 620 amp 1 2 100 0 ?0 1.0v 2.0v 40 ire modulation burst sync iae fc 2.0v 1.0v f c ?1khz v in d. g d. p digital output current test circuit v cc v rt v in v rb clk gnd i oh v oh + 2.0v 1.0v v cc v rt v in v rb clk gnd i ol v ol + 2.0v 1.0v electrical characteristics test circuit
?6 cxd1172am/ap analog input vi (1) vi (2) vi (3) vi (4) s (1) c (1) s (2) c (2) s (3) c (3) s (4) c (4) md (0) md (1) md (2) md (3) rv (0) rv (1) rv (2) rv (3) s (1) c (1) h (1) c (3) h (3) s (3) ld (?) ld (1) c (0) h (0) c (2) h (2) s (2) h (4) s (4) ld (?) ld (0) out (?) out (?) out (0) out (1) ld (2) external clock upper comparators block upper data lower reference voltage lower comparators a block lower data a lower comparators b block lower data b digital output timing chart 2
?7 cxd1172am/ap operation (see block diagram and timing chart) 1. cxd1172am/ap is a 2-step parallel system a/d converter featuring a 3-bit upper comparators group and 2 iower comparators groups of 3-bit each. the reference voltage that is equal to the voltage between vrt- vrb/8 is constantly applied to the upper 3-bit comparator block. voltage that corresponded to the upper data is fed through the reference supply to the lower data. 2. this ic uses an offset cancel type comparator and operates synchronously with an external clock. it features the following operating modes which are respectively indicated on the timing chart with s, h, c symbols. that is input sampling (auto zero) mode, input hold mode and comparison mode. 3. the operation of respective parts is as indicated in the chart. for instance input voltage vi (1) is sampled with the falling edge of the first clock by means of the upper comparator block and the iower comparator a block. the upper comparators block finalizes comparison data md (1) with the rising edge of the first clock. simultaneously the reference supply generates the lower reference voltage rv (1) that corresponded to the upper results. the lower comparator block finalizes comparison data ld (1) with the rising edge of the second clock. md (1) and ld (1) are combined and output as out (1) with the rising edge of the 3rd clock. accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. operation notes 1. v dd , vss to reduce noise effects, separate the analog and digital systems close to the device. for both the digital and analog v dd pins, use a ceramic capacitor of about 0.1f set as close as possible to the pin to bypass to the respective gnd's. 2. analog input compared with the flash type a/d converter, the input capacitance of the analog input is rather small. however it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. when driving with an amplifier of low output impedance, parasite oscillation may occur. that may be prevented by inserting a resistance of about 100 in series between the amplifier output and a/d input. 3. clock input the clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. reference input voltage between vrt to vrb is compatible with the dynamic range of the analog input. bypassing vrt and vrb pins to gnd, by means of a capacitor about 0.1f, stable characteristics are obtained. 5. timing analog input is sampled with the falling edge of clk and output as digital data with a delay of 2.5 clocks and with the following rising edge. the delay from the clock rising edge to the data output is about 18ns. 6. about latch up it is necessary that av dd and dv dd pins be the common source of power supply. this is to avoid latch up due to the voltage difference between av dd and dv dd pins when power is on. see "for latch up prevention" of cxd1172p/cxa1106p pcb description. (page 6, 7)
?8 cxd1172am/ap latch up prevention the cxd1172a is a cmos ic which requires latch up precautions. latch up is mainly generated by the lag in the voltage rising time of av dd (pins 10 and 14) and dv dd (pins 9 and 15), when power supply is on. 1. correct usage a. when analog and digital supplies are from different sources +5v av dd +5v av ss dv ss c14 dv dd digital ic c6 av ss dv ss av dd dv dd cxd1172a 14 15 9 10 8 16 b. when analog and digital supplies are from a common source (i) +5v av ss dv ss c14 dv dd digital ic c6 av ss dv ss av dd dv dd cxd1172a 14 15 9 10 8 16 (ii) +5v c6 av ss dv ss c14 dv dd digital ic av ss dv ss av dd dv dd cxd1172a 14 15 9 10 8 16
?9 cxd1172am/ap 2. example when latch up easily occurs a. when analog and digital supplies are from different sources +5v av dd +5v av ss dv ss dv dd digital ic c6 av ss dv ss av dd dv dd cxd1172a 14 15 9 10 8 16 b. when analog and digital supplies are from common source (i) +5v c6 av ss dv ss dv dd digital ic av dd av ss dv ss av dd dv dd cxd1172a 14 15 9 10 8 16 (ii) +5v av ss dv ss dv dd digital ic av dd av ss dv ss av dd dv dd cxd1172a 14 15 9 10 8 16
?10 cxd1172am/ap component side soldering side silk side analog c8 c9 c10 da out vr5 vr4 r10 r9 vr3 c2 c1 vr1 s in r1 c3 r3 q1 q2 r2 r4 r5 vr2 c4 q3 q4 q5 agnd c5 c6 r7 r8 c7 r6 analog a.gnd c11 c12 c13 dv dd av dd gnd +5v ?v c14 d6 d4 d2 d7 d5 d3 d1 d0 clk clk d7 d6 logic d5 d4 d3 d2 d1 d0 osc sw d.gnd r11 clk in a1106p d1172p 74s174 74s174 74hc04 2 1 3 6-bit, 20msps adc and dac evaluation board
?11 cxd1172am/ap package outline unit: mm cxd1172am package structure package material lead treatment lead material package weight sony code eiaj code jedec code sop-16p-l01 * sop016-p-0300-a copper alloy solder plating epoxy resin 16pin sop (plastic) 300mil 9.9 ?0.1 + 0.4 16 9 18 1.27 0.45 0.1 5.3 ?0.1 + 0.3 7.9 0.4 6.9 1.85 ?0.15 + 0.4 0.5 0.2 0.2 ?0.05 + 0.1 0.1 ?0.05 + 0.2 0.2g 0.15 m 0.12 cxd1172ap package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy 19.2 ?0.1 + 0.4 9 18 2.54 0.5 0.1 1.2 0.15 3.0 min 0.5 min 3.7 ?0.1 + 0.4 6.4 ?0.1 + 0.3 7.62 0.25 ?0.05 + 0.1 0?to 15 16 16pin dip (plastic) 1.0 g sony code eiaj code jedec code dip-16p-01 dip016-p-0300 similar to mo-001-ae 1.all mat surface type. two kinds of package surface: 2.all mirror surface type.

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